The present invention relates to static timing analysis of an integrated circuit design, and more specifically, to incremental common path pessimism analysis.
Timing analysis is performed during the various stages of digital integrated circuit (IC) or chip design to ensure that the end product will meet all timing requirements. A chip design is modeled as a timing graph with gate- and wire-pins denoted by timing nodes. Each connection from an input pin (source node) to an output pin (sink node) is denoted by a directed timing edge in the graph. Generally, timing analysis involves calculating delay through the edges or paths between a chip input and a chip output to determine the speed of propagation of signal transitions at different components (e.g., gates, wires, latches) of the chip. Generally, arrival time at a given point refers to either the latest (in LATE mode) or earliest (in EARLY mode) time at which the voltage at the point reaches half of the maximum voltage. To account for on-chip and environmental variations (e.g., temperature, battery level), statistical static timing analysis (SSTA) or another technique may be used to express arrival time as a range given by {early mode arrival time, late mode arrival time}. Many known tests (e.g., setup test, hold test) may be performed as part of the timing analysis. The tests examine the worst-case scenario in most cases. Thus, for example, the setup test determines if the late mode arrival time at the input of a data node of a device occurs before the early mode arrival time at the clock node so that the data is captured correctly. The issue of pessimism arises in timing analysis tests when early mode and late mode is considered for the same edge (path). For example, in the setup test example, if the data input and clock input shared an edge (a path segment), the test uses late mode arrival time with respect to the data input, which considers late mode delay through that edge, as well as early mode arrival time with respect to the clock input, which considers early mode delay through that same edge. This is referred to as common path pessimism (CPP). Common path pessimism removal (CPPR) is a technique for adjusting timing slack (crediting some time back to the edge) to account for the CPP associated with the edge.